A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology
نویسندگان
چکیده
منابع مشابه
A Novel Power Reduction Technique for Dual-threshold Domino Logic in Sub-65nm Technology
A novel technique for dualthreshold is proposed and examined with inputs and clock signals combination in 65nm dualthreshold footerless domino circuit for reduced leakage current. In this technique a p-type and an n-type leakage controlled transistor (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. A high-threshold tra...
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A new dual-threshold circuit technique is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type lea-kage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. ...
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--In this paper, we proposed a new dual threshold circuit technique for reduction of subthreshold and static power dissipation. When the scaling down technology the threshold voltage takes place, due to increasing the leakage current. In this method, n-type and ptype transistor are introduced between the pull up and pull down network, the gateof inserting transistors is connected to the respect...
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In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...
متن کاملAnalysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm
In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around ...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2013
ISSN: 0976-1527,0976-1357
DOI: 10.5121/vlsic.2013.4104